? semiconductor components industries, llc, 2014 october, 2014 ? rev. 4 1 publication order number: esd7181mu/d esd7181, szesd7181 low capacitance esd protection diodes micro?package diodes for esd protection the esd7181 is designed to protect voltage sensitive components that require ultra?low capacitance from esd and transient voltage events. excellent clamping capability, low capacitance, low leakage, and fast response time make these parts ideal for esd protection on designs where board space is at a premium. it has industry leading capacitance linearity over voltage making it ideal for rf applications. features ? low capacitance 0.3 pf (typical) ? low clamping voltage ? small body outline dimensions: (0.62 x 0.32 mm) ? 0201 ? low body height: 0.3 mm ? working voltage: 18.5 v ? low leakage < 1 na (typical) ? low insertion loss ? low dynamic resistance: < 1 ? iec61000?4?2 level 4 esd protection ? sz prefix for automotive and other applications requiring unique site and control change requirements; aec?q101 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant typical applications ? rf signal esd protection ? wireless charger ? rf switching, pa, and antenna esd protection ? near field communications maximum ratings (t a = 25 c unless otherwise noted) rating symbol value unit iec 61000?4?2 (esd) (note 1) air 15 kv iec 61000?4?2 (esd) (note 1) contact 12 kv iec 61000?4?5 (esd) (note 2) 1 a total power dissipation (note 3) @ t a = 25 c thermal resistance, junction?to?ambient p d r ja 250 400 mw c/w junction and storage temperature range t j , t stg ?55 to +150 c lead solder temperature ? maximum (10 second duration) t l 260 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. non?repetitive current pulse at t a = 25 c, per iec61000?4?2 waveform. 2. non?repetitive current pulse at t a = 25 c, per iec61000?4?5 waveform. 3. mounted with recommended minimum pad size, dc board fr?4 device package shipping ? ordering information http://onsemi.com ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our t ape and reel packaging specification s brochure, brd8011/d. esd7181mut5g x3dfn2 (pb?free) 15000 / tape & reel marking diagram x3dfn2 case 152af pin 1 2 = specific device code m = date code 2 m 12 *date code orientation and/or position may vary de - pending upon manufacturing location. SZESD7181MUT5G x3dfn2 (pb?free) 15000 / tape & reel
esd7181, szesd7181 http://onsemi.com 2 electrical characteristics (t a = 25 c unless otherwise noted) symbol parameter i pp maximum reverse peak pulse current v c clamping voltage @ i pp v rwm working peak reverse voltage i r maximum reverse leakage current @ v rwm v br breakdown voltage @ i t i t test current *see application note and8308/d for detailed explanations of datasheet parameters. bi?directional tvs i pp i pp v i i r i t i t i r v rwm v c v br v rwm v c v br electrical characteristics (t a = 25 c unless otherwise noted) parameter symbol condition min typ max unit ac working voltage v rwm ? ? 18.5 v breakdown voltage (note 4) v br i t = 1 ma 20.5 ? ? v ac reverse current i r v rvm = 18.5 v ? < 1 50 na clamping voltage (note 5) v c iec61000?4?2, 8 kv contact see figures 1 and 2 clamping voltage tlp (note 6) v c i pp = 8 a i pp = 16 a i pp = ?8 a i pp = ?16 a 37.7 40.4 ?38.4 ?41.1 v clamping voltage (note 6) vc i pp = 1 a @ 8/20 s ? 35 ? v junction capacitance c j v r = 0 v, f = 1 mhz v r = 0 v, f = 1 ghz 0.1 0.1 0.3 0.15 0.50 0.50 pf dynamic resistance r dyn tlp pulse 0.44 insertion loss f = 1 mhz f = 8.5 ghz ?0.045 ?0.335 db product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions. 4. breakdown voltage is tested from pin 1 to 2 and pin 2 to 1. 5. for test procedure see figures 3 and 4 and application note and8307/d. 6. ansi/esd stm5.5.1 ? electrostatic discharge sensitivity testing using transmission line pulse (tlp) model. tlp conditions: z 0 = 50 , t p = 100 ns, t r = 4 ns, averaging window; t 1 = 30 ns to t 2 = 60 ns. typical characteristics figure 1. typical iec61000?4?2 + 8 kv contact esd clamping voltage figure 2. typical iec61000?4?2 ? 8 kv contact esd clamping voltage time (ns) time (ns) 150 125 100 75 50 25 0 ?25 ?20 0 20 40 80 100 140 160 150 125 100 75 50 25 0 ?25 ?160 ?120 ?100 ?80 ?60 ?20 0 20 voltage (v) voltage (v) 60 120 175 ?40 ?140 175
esd7181, szesd7181 http://onsemi.com 3 iec 61000?4?2 spec. level test volt- age (kv) first peak current (a) current at 30 ns (a) current at 60 ns (a) 1 2 7.5 4 2 2 4 15 8 4 3 6 22.5 12 6 4 8 30 16 8 i peak 90% 10% iec61000?4?2 w aveform 100% i @ 30 ns i @ 60 ns t p = 0.7 ns to 1 ns figure 3. iec61000?4?2 spec figure 4. diagram of esd clamping voltage test setup 50 50 cable tvs oscilloscope esd gun the following is taken from application note and8308/d ? interpretation of datasheet parameters for esd devices. esd voltage clamping for sensitive circuit elements it is important to limit the voltage that an ic will be exposed to during an esd event to as low a voltage as possible. the esd clamping voltage is the voltage drop across the esd protection diode during an esd event per the iec61000?4?2 waveform. since the iec61000?4?2 was written as a pass/fail spec for larger systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. on semiconductor has developed a way to examine the entire voltage waveform across the esd protection diode over the time domain of an esd pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all esd protection diodes. for more information on how on semiconductor creates these screenshots and how to interpret them please refer to and8307/d.
esd7181, szesd7181 http://onsemi.com 4 figure 5. typical positive tlp iv curve figure 6. typical negative tlp iv curve current (a) voltage (v) 18 045 35 30 51015 25 20 current (a) voltage (v) 0 ?45 ?5 ?10 ?15 ?25 ?35 ?30 ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 note: tlp parameter: z 0 = 50 , t p = 100 ns, t r = 300 ps, averaging window: t 1 = 30 ns to t 2 = 60 ns. 16 14 12 10 8 6 4 2 0 40 ?20 ?40 transmission line pulse (tlp) measurement transmission line pulse (tlp) provides current versus voltage (i?v) curves in which each data point is obtained from a 100 ns long rectangular pulse from a charged transmission line. a simplified schematic of a typical tlp system is shown in figure 7. tlp i?v curves of esd protection devices accurately demonstrate the product?s esd capability because the 10s of amps current levels and under 100 ns time scale match those of an esd event. this is illustrated in figure 8 where an 8 kv iec 61000?4?2 current waveform is compared with tlp current pulses at 8 a and 16 a. a tlp i?v curve shows the voltage at which the device turns on as well as how well the device clamps voltage over a range of current levels. figure 7. simplified schematic of a typical tlp system dut l s oscilloscope attenuator 10 m v c v m i m 50 coax cable 50 coax cable figure 8. comparison between 8 kv iec 61000?4?2 and 8 a and 16 a tlp waveforms
esd7181, szesd7181 http://onsemi.com 5 typical characteristics figure 9. typical iv characteristics figure 10. typical cv characteristics voltage (v) v bias (v) 20 15 5 ?15 ?5 ?20 ?25 ?30 1.e?11 15 10 5 0 ?5 ?10 ?15 ?20 0 0.1 0.2 0.4 0.6 0.7 0.8 1.0 figure 11. typical insertion loss figure 12. typical capacitance over frequency frequency (hz) frequency (hz) 1.e+07 ?10 ?9 ?7 ?6 ?4 ?2 ?1 1 3.e+09 2.e+09 1.e+09 0.e+00 0 0.1 0.2 0.3 0.4 0.5 0.6 current (a) capacitance (pf) s21 (db) capacitance (pf) ?10 0 10 25 30 1.e?10 1.e?09 1.e?08 1.e?07 1.e?06 1.e?05 1.e?04 1.e?03 1.e?02 20 0.3 0.5 0.9 1.e+08 1.e+09 1.e+10 ?8 ?5 ?3 0
esd7181, szesd7181 http://onsemi.com 6 package dimensions x3dfn2, 0.62x0.32, 0.355p, (0201) case 152af issue o notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. a b e d bottom view b e 2x l 2x 2x 0.035 c top view 2x 0.035 c 2x a a1 0.05 c 0.05 c c seating plane side view dim min max millimeters a 0.25 0.33 a1 ??? 0.05 b 0.22 0.28 d 0.62 bsc e 0.32 bsc e 0.355 bsc l 0.17 0.23 mounting footprint* dimensions: millimeters 0.74 1 0.30 0.31 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 2 1 see application note and8398/d for more mounting details a m 0.05 b c a m 0.05 b c 2x 2x recommended pin 1 indicator (optional) on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other inte llectual property. a listing of scillc?s pr oduct/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typical s? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 esd7181mu/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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